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Peano
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Durham University maintains a hardware testbed suite that can be used for testing code on new hardware.
Further documentation can be found at https://cosma.readthedocs.io/en/latest/cosma.html.
The login nodes can be accessed at login8.cosma.dur.ac.uk. Further nodes can be accessed via these nodes. The following modules should be used for an Intel toolchain:
DINE (Durham Intelligent NIC Environment) is a small supercomputer attached to Cosma, which we use to prototype some of our algorithms. Access is through the Cosma loging nodes (login8.cosma.dur.ac.uk). As the login node and DINE feature the same generation of AMD chips, you can compile on the login node and ship the executable to DINE by submitting a slurm job to the bluefield1 partition. Should you choose to compile on DINE use the same modules as on the login node, which are:
There are a few things to consider whenever you use DINE:
ScoreP, Scalasca and Cube are installed for DINE. It supports gcc and this specific Intel toolchain. If you wish to use them load the modules:
ScoreP has to be installed anew for each toolchain, so it may not be installed for other toolchains.

mad07 is an IceLake server with Barlow Pass memory which is added to Cosma to facilitate benchmarking for the SKA project. It can be accessed with a slurm job to the cosma8-ska partition.
Previous modules/installations provided a oneAPI module. As this seems to be deprecated by Intel, one now has to load intel_comp and then the corresponding compiler and mpi.
The chip is from the Ice Lake-SP family, i.e. the generation released summer 2021. Without any further settings, OpenMP delivers a concurrency of around 11,170. This is due to two processors each featuring 28 cores with hyperthreading. I don't use hyperthreading usually, i.e. set
I thought they have 2x40 cores, but my benchmarks give me an OpenMP concurrency of 11,170, which suggests it has 112 cores in total. Does that mean we have 2x28 and hyperthreading is enabled?

These two servers feature the Genoa chipset. They can be accessed by submitting a slurm job to the cosma8-shm3 partition.
There are a few pitfalls with the AMD servers if you use the Intel toolchain. The Intel compiler does not recognise that the chip supports modern instruction sets. Notably, it is not aware of its AVX512 capabilities. Therefore, it produces machine code which does not use these features. You have to manually force it to produce the bytecode that you wanna have, by adding the compile flags
ExaParty also requires you to pass
to vectorisesome particular compute-heavy tasks (gravity).
Grace Hopper nodes can be accessed directly from the login node using
Code can be compiled here, or submitted as a slurm job to the gracehopper partition where it will run on a compute node.
The Grace Hopper build configuration is similar to any other build:
It is important to use cc90 here plus a reasonably new CUDA version. Furthermore, most systems deliver the NC++ pipeline with a rather old GCC/STL version. It might be necessary to load a newer GCC. Depending on the SLURM configuration, people might have to request GPUs explicitly when they want a Grace Hopper node.